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toshiba toshiba corporation 1/18 tlcs-90 series TMP90P800 the information contained here is subject to change without notice. the information contained herein is presented only as guide for the applications of our products. no responsibility is assumed by toshiba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of toshiba or others. these toshiba products are intended for usage in general electronic equipments (of?e equipment, communication equipment, measuring equipment, domestic electri?ation, etc.) please make sure that you consult with us before you use these toshiba products in equip- ments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traf? signal, combustion control, all types of safety devices, etc.). toshiba cannot accept liability to any damage which may occur in case these toshiba products were used in the mentioned equipments without prior consultation with toshiba. cmos 8?it microcontrollers TMP90P800n/TMP90P800f 1. outline and characteristics the TMP90P800 is a system evaluation lsi having a built in one-time prom for tmp90c400/800. a programming and veri?ation for internal prom is achieved by using a general eprom programmer with an adapter socket. the function of this device is exactly same as the tmp90c400 by programming to the internal prom. the differences between TMP90P800 and tmp90c400 are the memory size (rom/ram). the following are the memory map of TMP90P800 and tmp90c400. the TMP90P800n is in a shrink dual inline package (sdip64-p-750). the TMP90P800f is in a quad flat package (qfp64-p- 1420a). parts no. rom ram package adapter socket no. TMP90P800n otp 8192 x 8bit 256 x 8bit 64-sdip bm1142 TMP90P800f 64-fp bm1147 www.datasheet.in
2/18 toshiba corporation TMP90P800 figure 1. TMP90P800 block diagram www.datasheet.in
toshiba corporation 3/18 TMP90P800 2. pin assignment and functions the assignment of input/output pins, their names and functions are described below. 2.1 pin assignment figure 2.1 shows pin assignment of the TMP90P800 . figure 2.1 (1). pin assignment (64-sdip) www.datasheet.in
4/18 toshiba corporation TMP90P800 figure 2.1 (2). pin assignment (64-fp) www.datasheet.in
toshiba corporation 5/18 TMP90P800 2.2 pin names and functions the TMP90P800 has mcu mode and prom mode. (1) mcu mode (the tmp90c400 and the TMP90P800 are pin compatible). table 2.2.1 pin names and functions (1/2) pin name no. of pins i/o 3 states function p00 ~ p07 /ad0 ~ ad7 8 i/o port 0: 8-bit i/o port that allows selection of input/output on bit basi.s 3 states address/data bus: also functions as the lower 8 bits bidirectional data bus for external memory. p10 ~ p17 /a8 ~ a15 8 i/o port 1: 8-bit i/o port that allows selection on bit basis. output address bus: the upper 8 bits address bus for external memory. p20 ~ p23 4 i/o port 20 ~ 23: 4-bit i/o port with a pull-up resistor that allows selection on bit basis p24 /nmi 1 i/o port 24: 1-bit i/o port with a pull-up resistor. input non-maskable interrupt request pin: falling edge interrupt register pin. p25 /w ait 1 i/o port 25: 1-bit i/o port with a pull-up resistor. input wait: input pin for connecting slow speed memory of peripheral lsi p26 /rd 1 output port 26: 1-bit output port output read: generates strobe signal for reading external memory. p27 /wr 1 output port 27: 1-bit output port output write: generates strobe signal for writing into external memory p30 /into 1 i/o port 30: 1-bit i/o port with a pull-up resistor. input interrupt request pin 0: interrupt request pin (level/rising edge is programmable) p31 /int1 1 i/o port 31: 1-bit i/o port with a pull-up resistor. input interrupt request pin 1: rising edge interrupt request pin p32 /t10 1 i/o port 32: 1-bit i/o port with a pull-up resistor. input timer input 0: counter input pin for timer 0 p33 /ti2 1 i/o port 33: 1-bit i/o port with a pull-up resistor. output timer input 2: counter input pin for timer 2 www.datasheet.in
6/18 toshiba corporation TMP90P800 table 2.2.1 pin names and functions (2/2) (2) prom mode (note) be ?ed to ??level when the 400-mode bit or the security bit is programmed. p35 /rxd 1 i/o port 35: 1-bit i/o port with a pull-up resistor. i/o receive serial data p36 /sclk 1 i/o port 36: 1-bit i/o port with a pull-up resistor. output serial clock output p37 txd 1 i/o port 37: 1-bit i/o port with a pull-up resistor. output transmitter serial data p40 ~ p47 8 i/o port 4: 8-bit i/o port that allows i/o selection on bit basis. p50 ~ p57 8 i/o port 5: 1-bit i/o port with a pull-up resistor. p60 ~ p67 8 i/o port 6: 8-bit i/o port that allows i/o selection on bit basis. ale 1 output address latch enable signal: the negative edge of ale supplies an address latch timing for external memory access. ea 1 input external access: connects with v cc pin in the TMP90P800 built rom is used. clk 1 output clock output: generates clock pulse at 1/4 frequency of clock oscillation. it is pulled up i nternally during resetting. reset 1 input reset: initializes the TMP90P800. x1/x2 2 i/o pin for quartz crystal or ceramic resonator v cc 1 power supply (+5v) v ss 1 ground (0v) table 2.2.2 pin function name no. of pins i/o function pin name (mcu mode) a7 ~ a0 8 input program memory address input p67 ~ p60 a12 ~ a8 5 input p14 ~ p10 a15 ~ a13 3 input be fixed to ??level. (note) p17 ~ p15 d7 ~ d0 8 i/0 data input/output p07 ~ p00 oe 1 input output enable input p26 ce 1 input chip enable input p27 vpp 1 power supply 12.5v/5v (programming power supply) ea vcc 1 power supply 5v vss 1 power supply 0v pin name no. of pins i/o pin setting p20 ~ p23 4 input be fixed to ??level. nmi 1 input be fixed to ??level. wait 1 input be fixed to ??level. p30 ~ p34 5 input be fixed to ??level. p35, p36 2 input be fixed to ??level. p37 1 input be fixed to ??level. p40 ~ p47 p50 ~ p57 8 8 input be fixed to ??level. reset 1 input be fixed to ??level. clk 1 input be fixed to ??level. ale 1 output open x1 1 input resonator connection pin x2 1 output www.datasheet.in
toshiba corporation 7/18 TMP90P800 3. operation the TMP90P800 is the otp version of the tmp90c400 that is replaced an internal rom from mask rom to eprom. the function of TMP90P800 is exactly as that of tmp90c400 except the internal rom/ram size. refer to the tmp90c400 except the functions which are not described this section. the following is an explanation of the hardware con?uration and operation in the relation to the TMP90P800. the TMP90P800 has an mcu mode and a prom mode. 3.1 mcu mode (1) mode setting and function the mcu mode is set by opening the clk pin (output status). in the mcu mode, the operation is the same as that of tmp90c400. (2) memory map figure 3.1 shows the memory map of TMP90P800, and the accessing area by the respective addressing mode. www.datasheet.in
8/18 toshiba corporation TMP90P800 figure 3.1. TMP90P800 memory map www.datasheet.in
toshiba corporation 9/18 TMP90P800 3.2 prom mode (1) mode setting and function prom mode is set by setting the reset and clk pins to the ??level. the programming and veri?ation for the internal prom is achieved by using a general eprom programmer with the adaptor socket. the device selection (rom type) should be ?7256?with following conditions. size: 256kbit (32k x 8bit) vpp: 12.5v tpw: 1ms figure 3.2 shows the setting of pins in prom mode. figure 3.2. prom mode pin setting (2) programming flow chart the programming mode is set by applying 12.5v (pro- gramming voltage) to the vpp pin when the following pins are set as follows, (vcc : 6.0v) *these conditions can be ( reset : ??level) obtained by using adaptor (clk : ??level) socket. after the address and data have been ?ed, a data on the data bus is programmed when the ce pin is set to ?ow?(1ms plus is required). general programming procedure of an eprom programmer is as follows, ?write a data to a speci?d address for 1ms. ?verify the data. if the read-out data does not match the expected data, another writing is performed until the correct data is written (max. 25 times). after the correct data is written, an additional writing is performed by using three times longer programming pulse width (1ms x programming times), or using three times more programming pulse number. then, verify the data and increment the address. the veri?ation for all data is done under the condition of vpp = vcc = 5v after all data were written. figure 3.3 shows the programming ?w chart. www.datasheet.in
10/18 toshiba corporation TMP90P800 figure 3.3. flow chart www.datasheet.in
toshiba corporation 11/18 TMP90P800 (3) the 400-mode bit and the security bit the TMP90P800 has the 400-mode bit and the security bit in prom cell. if the 400-mode bit is programmed to ?? the TMP90P800 functions as its memory size is same as tmp90c400 (rom: 0000h ~ 0fffh, ram: ff00h ~ ff7fh). if the security bit is programmed to ?? the content of the prom is disable to read in prom mode. if both the 400-mode bit and the security bit is programmed to ?? the memory size is as same as tmp90c400 and its content of the prom is disable to read. how to program the 400-mode bit or the security bit. 1) connect a13, a14 and a15 pins to vcc. [otherwise connect them to gnd to program prom. (address 0000h ~ 1fffh)] 2) set programming address to 0000h. 3) to program the 400-mode bit, set d1 to ?? 4) to program the security bit, set d0 to ?? 5) set d2 ~ d7 to ??respectively. the following table shows the 8-bit data to program the 400-mode bit or the security bit. table 3.1 data to program bit to program d0 ~ d7 a0 ~ a12 a13, a14, a15 the 400-mode bite the security bit the 400-mode bit and the security bit fdh feh fch all ? all ? prom (0000h ~ 1fffh) all ? www.datasheet.in
12/18 toshiba corporation TMP90P800 4. electrical characteristics TMP90P800n/TMP90P800f note: i dar is guaranteed for a total of up to 8 optional ports. 4.1 absolute maximum ratings symbol parameter rating unit v cc supply voltage -0.5 ~ + 7 v v in input voltage -0.5 ~ v cc + 0.5 v p d power dissipation (ta = 85 c) f 500 mw n 600 t solder soldering temperature (10s) 260 c t stg storage temperature -65 ~ 150 c t opr operating temperature -40 ~ 85 c 4.2 dc characteristics v cc = 5v 10% ta = -40 ~ 85 c (1 ~ 10mhz) ta = -20 ~ 70 c (1 ~ 12.5mhz) symbol parameter min max unit test conditions v il input low voltage (p0) -0.3 0.8 v v il1 p1, p2, p3, p4, p5, p6 -0.3 0.3v cc v v il2 reset , nmi -0.3 0.25v cc v v il3 ea -0.3 0.3 v v il4 x1 -0.3 0.2v cc v v ih input high voltage (p0) 2.2 v cc + 0.3 v v ih1 p1, p2, p3, p4, p5, p6 0.7v cc v cc + 0.3 v v ih2 reset , nmi 0.75v cc v cc + 0.3 v v ih3 ea v cc - 0.3 v cc + 0.3 v v ih4 x1 0.8v cc v cc + 0.3 v v ol output low voltage 0.45 v i ol = 1.6ma v oh v oh1 v oh2 output high voltage 2.4 0.75v cc 0.9v cc v v v i oh = -400 m a i oh = -100 m a i oh = -20 m a i dar darlington drive current (8 i/o pins) (note) -0.1 -3.5 ma v ext = 1.5v r ext = 1.1k w i li input leakage current 0.02 (typ) 5 m a 0.0 vin v cc i lo output leakage current 0.05 (typ) 10 m a 0. 2 vin v cc - 0.2 i cc operating current (run) idle 1 idle 2 20 (typ) 1.5 (typ) 6 (typ) 40 5 15 ma ma ma tosc = 10mhz (25%up @12.5mhz) stop (ta = -40 ~ 85 c) stop (ta = 0 ~ 50 c) 0.05(typ) 50 10 m a m a 0.2 vin v cc - 0.2 v stop power down voltage (@stop) 2 ram back up 6v v il2 = 0.2v cc , v ih2 = 0.8v cc r rst reset pull up register 50 150 k w cio pin capacitance 10 pf testfreq = 1mhz v th schmitt width reset , nmi 0.4 1.0 (typ) v www.datasheet.in
toshiba corporation 13/18 TMP90P800 ac measuring conditions output level: high 2.2v/low 0.8v, c l = 50pf (however, cl = 100pf for ad0 ~ 7, a8 ~ 15, ale, rd , wr ) input level: high 2.4v/low 0.45v (ad0 ~ ad7) high 0.8v cc /low 0.2v cc (excluding ad0 ~ ad7) 4.3 ac characteristics v cc = 5v 10% ta = -40 ~ 85 c (1 ~ 10mhz) ta = -20 ~ 70 c (1 ~ 12.5mhz) symbol parameter variable 10mhz clock 12.5mhz clock unit min max min max min max t osc oscillation cycle ( = x) 80 1000 100 80 ns t cyc clk period 4x 4x 400 320 ns t wh clk high width 2x - 40 160 120 ns t wl clk low width 2x - 40 160 120 ns t al a0 ~ 7 effective address ? ale fall 0.5x - 15 35 25 ns t la ale fall ? a0 ~ 7 hold 0.5x - 15 35 25 ns t ll ale pulse width x - 40 60 40 ns t lc ale fall rd /wr fall 0.5x - 30 20 10 ns t cl rd /wr ? ale rise 0.5x - 20 30 20 ns t acl a0 ~ 7 effective address ? rd /wr fall x - 25 75 55 ns t ach upper effective address ? rd /wr fall 1.5x - 50 100 70 ns t ca rd /wr fall ? upper address hold 0.5x - 20 30 20 ns t adl a0 ~ 7 effective address ? effective data input 3.0x - 35 265 205 ns t adh upper effective address ? effective data input 3.5x - 55 295 225 ns t rd rd fall ? effective data input 2.0x - 50 150 110 ns t rr rd pulse width 2.0x - 40 160 120 ns t hr rd rise ? data hold 0 0?ns t rae rd rise ? address enable x - 15 85 65 ns t ww wr pulse width 2.0x - 40 160 120 ns t dw effective data ? wr rise 2.0x - 50 150 110 ns t wd wr rise ? effective data hold 0.5x - 10 40 30 ns t ackh upper address ? clk fall 2.5x - 50 200 150 ns t ackl lower address ? clk fall 2.0x - 50 150 110 ns t ckha clk fall ? upper address hold 1.5x - 80 70 40 ns t cck rd /wr ? clk fall x - 25 75 55 ns t ckhc clk fall ? rd /wr rise x - 60 40 20 ns t dck valid data clk fall x - 50 50 30 ns t cwa rd /wr fall ? valid wait x - 40 60 40 ns t awal lower address ? valid wait 2.0x - 70 130 90 ns t wah clk fall ? valid wait hold 0 0?ns t awah upper address ? valid wait 2.5x - 70 180 130 ns t cpw clk fall ? port data output x + 200 300 280 ns t prc port data input ? clk fall 200 200 200 ns t cpr clk fall ? port data hold 100 100 100 ns www.datasheet.in
14/18 toshiba corporation TMP90P800 4.4 zero-cross characteristics v cc = 5v 10% ta = -40 ~ 85 c (1 ~ 10mhz) ta = -20 ~ 70 c (1 ~ 12.5mhz) symbol parameter condition min max unit v zx zero-cross detection input ac coupling c = 0.1 m f 1 1.8 vac p-p a zx zero-cross accuracy 50/60hz sine wave 135 mv f zx zero-cross detection input frequency 0.04 1 khz 4.5 serial channel timing-i/o interface mode v cc = 5v 10% ta = -40 ~ 85 c (1 ~ 10mhz) cl = 50pf ta = -20 ~ 70 c (1 ~ 12.5mhz) symbol parameter variable 10mhz clock 12.5mhz clock unit min max min max min max t scy serial port clock cycle time 8x 800 640 ns t oss output data setup sclk rising edge 6x - 150 450 330 ns t ohs output data hold after sclk rising edge 2x - 120 80 40 ns t hsr input data hold after sclk rising edge 0 0?ns t srd sclk rising edge to input data valid 6x - 150 450 330 ns 4.6 8-bit event counter v cc = 5v 10% ta = -40 ~ 85 c (1 ~ 10mhz) ta = -20 ~ 70 c (1 ~ 12.5mhz) symbol parameter variable 10mhz clock 12.5mhz clock unit min max min max min max t vck ti2 clock cycle 8x + 100 900 740 ns t vckl ti2 low clock pulse width 4x + 40 440 360 ns t vckh ti2 high clock pulse width 4x + 40 440 360 ns 4.7 interrupt operation v cc = 5v 10% ta = -40 ~ 85 c (1 ~ 10mhz) ta = -20 ~ 70 c (1 ~ 12.5mhz) symbol parameter variable 10mhz clock 12mhz clock unit min max min max min max t intal nmi , int0 low level pulse width 4x 400 320 ns t intah nmi , int0 high level pulse width 4x 400 320 ns t intbl int1 low level pulse width 8x + 100 900 740 ns t intbh int1 high level pulse width 8x + 100 900 740 ns www.datasheet.in
toshiba corporation 15/18 TMP90P800 4.8 read operation (prom mode) tcyc = 400ns (10mhz clock) a = 200ns 4.9 programming operation (prom mode) dc characteristic, ac characterisc ta = -40 ~ 85 c vcc = 5v 10% symbol parameter condition min max unit v pp v ih1 v il1 v pp read voltage input high voltage (a0 ~ a15, ce , oe ) input low voltage (a0 ~ a15, ce , oe ) 4.5 0.7 x v cc -0.3 5.5 vcc + 0.3 0.3 x v cc v v v t acc address to output delay c l = 50 p f 2.25tcyc + a ns dc characteristic, ac characteristic ta = 25 5 c vcc = 6v 0.25v symbol parameter condition min typ max unit v pp v ih v il v ih1 v il1 i cc i pp programming voltage input high voltage (d0 ~ d7) input low voltage (d0 ~ d7) input high voltage (a0 ~ a15, ce , oe ) input low voltage (a0 ~ a15, ce , oe ) v cc supply current v pp supply current t osc = 10mhz v pp = 13.00v 12.25 0.2v cc + 1.1 -0.3 0.7v cc -0.3 12.50 12.75 v cc + 0.3 0.2v cc - 0.1 v cc + 0.3 0.3v cc 50 50 v v v v v ma ma t pw ce programming pulse width c l = 50 p f 0.95 1.00 1.05 ms www.datasheet.in
16/18 toshiba corporation TMP90P800 4.10 i/o interface mode timing www.datasheet.in
toshiba corporation 17/18 TMP90P800 4.11 timing chart www.datasheet.in
18/18 toshiba corporation TMP90P800 4.12 read operation timing chart (prom mode) 4.13 programming operation timing chart (prom mode) www.datasheet.in

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